Digital products inspection system

ABSTRACT

A Digital Product Inspection System using a digital pseudorandom generator in combination with a charactertistic of the product being inspected to produce a unique set of data combinations which when compared with previously taken data from the test of a &#39;&#39;&#39;&#39;known good unit&#39;&#39;&#39;&#39; will provide an output indicating whether or not the characteristic of the unit under test is within acceptable limits.

United States Patent [151 3,651,315

Collins 5] Mar. 21, 1972 s41 DIGITAL PRODUCTS INSPECTION 561 ReferencesCited SYSTEM I UNITED STATES PATENTS [72] Invent: Dallas 2,996,6668/1961 Baker ..235/15L3l x [73] Assignee: Collins Radio Company, CedarRapids, 3,082,374 3/1963 Buuck 235/ 151.31 X Iowa 3,246,240 4/1966Arnold et a1... ..324/173 [22] Filed May 14 1970 3,471,779 10/1969 Ley..235/15131X [21] App1.No.: 37,320 Primary Examiner-Malcolm A. MorrisonAssistant Examiner-R. Stephen Dildine, Jr. Related Application DataAttorney-Bruce C. Lutz and Robert J. Crawford [63] Continuation-impartof Ser. No. 33,018, Apr. 29,

1970, abandoned. [57] ABSTRACT [52] U s 235/151 31 324/73 R 324/73 AT ADigital Product Inspection System using a digital pseudo- 324/73 randomgenerator in combination with a charactertistic of the s x 1 im. Cl..G01r 31/28 GOlr 17/02 Pmduc beirg inspected Pmdu a unique dam 58 Fieldof Search ..235 151.31; 324/73 R, 73 AT, binamns which when withPrevmusly take" 73 PC from the test of a known good unit will provide anoutput indicating whether or not the characteristic of the unit under 7test is within acceptable limits.

31 Claims, 17 Drawing Figures CONTROL LOGIC FOR esmaaaa I121???-,;,;,',I,,%ffi8" OF TESTIN N G AND TESTING CZWT AQ I LIRIC INPUT FROMMASTER [I02 REGISTER CONTROL LOGIC SERIAL-TO- 1 PARALLEL I05 DOUBLELINES '03 CONVERTER INDICATE PARALLEL WORD I TRANSMISSION UN FIOO (H4109 KIIBQERZEF; (I01 T UNDER UUT TEST CL0CK PULSE TRANSFER COMPAREINDICATION DATA (UUT) SOURCE FUNCTION FUNCTION 9 PROCESSOR H2 REMOTETERMINAL we TEL E 'I' II EGJI RITER I08 FROM MASTER OUTPUT CONTROL LOGICHo f' REGISTER PARALLEL FROM MASTER TO SER'AL CONVERTER CONTROL LOGICFROM MASTER CONTROL LOGIC FROM MASTER CONTROL LOGIC PAIENTEDIIIR2I I9723.651315 I SHEET UZUF I3 sET INITIALIZATION COUNTER To I NUMBER OF STEPINITIALIZING WORDS TO BE SUPPLIED DETERMINE 1* CYCLING COUNT I2s STEP 2OF CYCLE COUNTER AND SET To ZERO SET SAMPLE 41 coUNTER TO -I2T STEPDESIRED NUMBER OF SAMPLES -I2s SEND NEXT INITIALIZING DATA 4* mm ToPROPER STEP 4 INPUT REGISTER Ii BEGIN [I30 STEP 6 CHARACTERIZATION GATECONTENT FOR LAST OFOYCEISNICNG 0F 'NPUT INITIALIZING woRD REG'STERSINH'IAFZAT ION COUNT T0 UUT COUNTER NUMBER OF 0 CYCLES WITH CYCLEcoUNTER sTE 'r SAMPLE COUNTER DECREMENTS EACH COMPLETE CYCLING OF CYCLECOUNTER END OF TEST FIG. 2

INVENTOR.

A RTHUR A. vCOLL/N5 A TTORNEY PATENTEIIIIIIII2I I972 8,651,315

SHEEI 0U 0F 13 204- l K206 205 BggFC 200 MAGNETIC DATA 202 TAPEPROCESSOR r m'g CONTROL UN|T COMPARE RANSFER TEST (MTCU) 2|O\ (UUT) 1INITIALIZATION MODE I FIG. 4A

r I 20I' l f I 206' 205' r- I 200% 2|0 202 203 I MTCU COMPARE XFR UUTPROCESSOR I CONTROL LOGIC 1 CHARACTERIZATION MODE 1 l FIG. 4B

2II' L 7 KZOIH I 209 u I r LOGIC 207 I PROCESSO 4 am" 1 I MTCU COMPARE xFR UUT .K II I II 204 203 TESTING MODE 208 I I FIG. 4C

INVENTOR.

ARTHUR A. COLL/NS BY 7 A TTORNfY PAIENTEDMIIRZI m 3.651 ,315

' SHEET 08 0F 13 252 40 VARIABLE 0 RATE CLOCK PULSE souRcE 330 FORGHARADTER- IzATIoN AND 403 TESTING AND I 254' @IRB'III 427 40| OUTPUTREGISTERS CHARACTIZATION AND T STING MODES 425 404 407 SIO GHA RA IgTERIz T N MO +34 405 GA'T'ES I TO 4 3 WORD 'S40 T0 INPUT R IISII'BERE sPROCESSOR l R TO OMPARE Z 40s FUNCTION w 406 433 456' 2 I COMPARISONCOMPLETED l- R 436 E- I I 5) I SAMPLE 42s STROBE SIGNAL g I585 3 E LEENB T E S95 I 25o UUT MEANS FOR I AND SETTING SINGLE O I OUTPUT BIT INFIRST 9 I f REG'STERS STAGE OF SHIFT REGISTER 123g 409 IOO J 430 I l 4HF270 4'8 CHARACTERIZATION SELECTOR I AND TESTING I MEANS r MODES 325(COUNT 0-3) F420 A FROM COUNTER FIG. 8' IIIIIAI; K MODE 'Dlkfig RESET TozERo INVENTOR.

' ARTHUR A. COLL/N8 ATTORNEY PATENTEDHARZI m2 SHEET 120F113 B, .NB

g wFDa .PDO mmw otw INVENTOR.

ARTHUR A. COLL/N5 ATTORNEY DIGITAL PRODUCTS INSPECTION SYSTEM.

The present application is a continuation-in-part of a previously filedcopending application by the present inventor and assigned to the sameassignee as the present application. The copending application was filedon Apr. 29, 1970 with Ser. No. 33,018 and titled Digital ProductsInspection System," and now abandoned.

This invention relates generally to means for digitally testing varioustypes of electronics products and more specifically it relates to ameans and a method of digitally testing electronic products by means ofa very large number of pseudo-random data words being circulatedtherethrough at a high rate of speed and being checked periodically forcoincidence against a known truth table of data words.

INTRODUCTION One of the major problems involved in the manufacture ofelectronic components, circuits, equipments, and systems is the testingthereof. Such testing must be made on substantially every electronicproduct, including for example, integrated circuits, MOS circuits,circuits comprised of discrete components as well as the discretecomponents themselves, equipments such as radios, systems comprised ofvarious black boxes which cooperate with each other, and even dataprocessor systems made up of a plurality of data processors andperipheral equipment. One means by which such testing has beenaccomplished in the prior art is by supplying to the electronic device,whether it be a component or a data processor, a series ofpre-programmed data words with the responding output data words fromsaid electronic device then being compared with a known good series ofsuch responsive data words.

Because of the very large number of different electronic productsmanufactured by many companies, a great deal of engineering time isrequired to prepare the necessary testing programs. The number, lengthand frequency of the data words supplied to any given electronic unitunder test (UUT) is determined by the nature of the unit under test. Forexample, it is apparent that a much more elaborate testing program mustbe employed in testing an electronic data processor than would berequired to test simple AND gate logic circuits.

Once the test program for a given electronic device has been determinedby an engineer, such testing program is then applied to a known goodelectronic device and the results thereof recorded in some suitablestorage means, such as a magnetic tape. Subsequently the same testprogram is supplied the electronic devices to be tested (of the sametype) and the results thereof compared with the results obtained fromthe known good unit. Often the test data words are supplied both to theknown good unit and to the subsequent units under test from a dataprocessor.

Supplying words to a unit under test directly from a data processorinvolves several problems, however. One of these problems is the factthat the speed with which the data word can be supplied to the unitunder test is determined by the rate at which the data processor candeliver words, i.e., the access time to the bulk storage in the dataprocessor system in which the data words are stored. It is possible toutilize a sophisticated, high-speed data processor which will deliverthe words at a fast enough rate to accomplish the desired results.However, such an expedient would usually involve the use of an expensivedata processor over extensive periods of time, since each data wordsupplied to the unit under test would be supplied from the dataprocessor. A second problem arising when the processor supplies all ofthe data test words is that the test words must be originally programmedby an engineer, supplied to the data processor, and then subsequentlysupplied to the unit under test. Because an engineers time is involvedin initially programming the data test words to be supplied to the unitunder test, the number of words supplied to the test unit are usuallysomewhat limited, thus limiting the scope of the test.

On the other hand, if a relatively low speed data processor is employedto supply the test words to the unit under test, then a problem ofbandwidth arrives. More specifically the testing of many electronicdevices involves a matter of reaction time or recovery rate. Forexample, it may be desired that a counter be able to count at a certainrate. To effectively test the ability of the counter to count at thisdesired rate, it is necessary that data words be supplied to the unitunder test at the rate at which the counter is to count. If the dataprocessor is incapable of supplying data words to the counter at such adesired rate, then it is not possible to effectively test the counter.

OBJECTS A primary object of the invention is a high-speed digitaltesting method device capable of transferring a large number of datawords through the unit under test substantially independently of a dataprocessor, thereby substantially eliminating any correlation between therate of transfer of data words through the unit under test and theoperating speed of the data processor.

A second object of the invention is a high-speed digital testing systemin which only a relatively small amount of engineering time is requiredto prepare the programming necessary for a given test.

A final object of the invention is a method for testing electronicdevices by passing a very large number of test data words through theunit under test at a high word rate, independently of bulk storage andindependently of the operating speed of a data processor, and further,checking the accuracy of the unit under test by periodically comparingthe circulating data word with corresponding data words previouslystored from a similar test made on a known good electronic device of thetype being tested.

STATEMENT OF INVENTION The invention includes both a method of and theapparatus for performing the method. The apparatus comprises a group oflogic circuits which are arranged, under control of a master controllogic means, into three different logic configurations, as follows:

I. Initialization mode of operation.

2. Characterization mode of operation.

3. Testing mode of operation.

In performing the process the apparatus is caused to assume theaforementioned modes of operation in the following sequence:

1. Initialization mode of operation for known good unit.

2. Characterization mode of operation for known good unit.

3. Initialization mode of operation for unit under test.

4. Testing mode of operation for the unit under test.

PROCESS INVENTION In accordance with the process invention, a known goodunit of the type to be tested is obtained by statistical or analyticaltesting methods. The statistical method would involve testing aplurality of units and deciding that the largest group of unitscomplying with certain requirements must comprise known good units. Theanalytical methods can be quite varied, but in essence they comprise thederivation of a truth table and the inspection of the device in a mannercompatible with the desired truth table results. The units whichfavorably compare in test results to the generated truth table will thenbe assumed to be known good units. However, this will not be delved intofurther since the means for obtaining a known good unit is known in theart and is not pertinent to the practice of the present invention.

A known good unit is first supplied with a predetermined sequence ofinitializing data words from a data processor which functions to placethe known good unit in a predetermined condition. The foregoing occursduring the initialization mode of operation.

Upon completion of initialization, the characterization mode ofoperation begins. During the characterization mode, a transfer functionis connected across the known good unit and the data word is circulatedat a high rate of speed around the loop known herein as the transferloop and comprising the known good unit and the transfer function, withsaid data word being altered each time it passes through the transferfunction. At periodic intervals, which may be every Nth circulation ofthe data word around the transfer loop, said data word is sampled andsupplied to the data processor where it is stored. Thus at the end ofthe characterization mode of operation, there is stored in the dataprocessor system a truth table of sampled data words taken from a unitknown to be good.

Next, a unit to be tested, referred to herein as the UUT (unit undertest), is then connected into the testing apparatus and initialized inprecisely the same manner as was the known good unit, so that at the endof initialization the UUT is in exactly the same state as was the knowngood unit at the end of its initialization. The test cycle is then begunand is performed in a manner similar to the characterization of theknown good unit. More specifically, in the test cycle the transferfunction is connected across the UUT and the data word is circulatedthrough the transfer loop comprising the UUT and the transfer function.

Every Nth circulation (or other appropriate time interval fixed orvaried in a predetermined manner) of the said data word, said data wordis sampled and supplied to a compare function, to which is also suppliedthe samples of the known good unit which are contained in the truthtable stored in the data processor system. As long as coincidence occursbetween the sampled data words from the unit under test (UUT) and thecorresponding words from the truth table in the data processor, the unitis deemed to be good. However, when a non-coincidence between these twowords occurs the unit is adjudged to be defective and the test isaborted, with appropriate signals being given to the data processor andto a human operator.

APPARATUS INVENTION Structurally, the invention comprises a test stationinto which either the known good unit or a UUT is placed, andelectronically connected into the testing apparatus. The structure ofthe invention further comprises a number of logical elements which arecaused to assume various modes of operation in accordance with thesequence of the process invention as listed above, and under the generalcontrol of a master control logic means which operates in conjunctionwith a data processor. These other logic elements of the inventioncomprise a transfer function means, a compare function means, andappropriate counting and storage means within the master control logicwhich will respond to certain instructions from the data processor todetermine the various parameters of the test. Such parameters includethe number of steps in the initialization mode of operation, the numberof samplings in the characterization and testing modes of operation, thenumber of circulations of the data word between each sampling, and therate of speed of circulation of the data word.

The transfer function, the compare function, and the master control areidentified herein collectively as the feedback sequence control circuit,since they operate together to control the flow and processing of datain the system.

In the initialization mode of operation, the master control logicfunctions to enable gating means to connect the output of said dataprocessor to the master control logic and also to the electronic devicein the test station, which can be either the known good unit or the UUT.The data processor will then supply a series of instruction words to themaster control logic to set the various counting and storage meanstherein, thereby determining the parameters of the initialization,characterization, and testing modes of operation which are to follow.The master control logic will also function to gate a series ofinitialization data words from the data processor to the device in thetest station to initialize said device to a known condition.

During the initialization mode, the logical configuration of theapparatus is such that the transfer function and the compare functionare both disabled, and further is such that there are no data wordstransferred from the device being tested back to the data processor.

In the characterization mode of operation, the transfer function means,under control of the master control logic, is connected across theelectronic device which has been initialized. Timing means, also undercontrol of the master control logic, functions to circulate an initiallydetermined data word around the transfer loop comprising the'electronicdevice and the transfer function. This circulation of such a data wordis at a much higher rate of speed than can be obtained in the transferof data words from the data processor to the electronic device andfurther, is self changing in a pseudo-random manner. This pseudo-randommanner is repeatable for a complete test cycle for each unit testedwhich responds in the same manner as the known good unit.

The master control logic means further comprises structure for samplingthe circulating data word every Nth circulation thereof and forsupplying said sampled data word to the data processor, which in turnstores said sampled data words in the same order as they are received inappropriate bulk storage means such as main core memory or magnetictape. Such storage of the sampled data words constitutes a truth tablewhich is employed, during the testing mode of operation, as a referenceto determine if any given UUT is defective or good.

In the testing mode of operation a unit under test (UUT) is placed inthe test station of the testing apparatus. Initialization of the UUT isfirst obtained in the same manner as discussed in connection with theknown good unit so that testing of the UUT will commence with the UUTbeing in exactly the same initial condition as was the known good unit.

In the testing mode of operation, the master control logic functions toenable appropriate gating means to connect the transfer functions acrossthe UUT and to provide the aforementioned timing means to circulate aninitially determined data word around the transfer loop comprising theUUT and the transfer function. The said initially determined data wordis the same as was employed at the beginning of characterization of theknown good unit. Further the rate of speed of circulation of the dataword is made identical to that employed during characterization of saidknown good unit.

The master control logic further functions to sample the circulatingdata word every Nth circulation thereof so that the samplings of the UUToccur at times which correspond precisely to the times of samplings madeof the known good unit during the characterization mode of operation.Thus, if the UUT and the known good unit are the same, within giventolerances, the sequence of sampled data words being obtained currentlyduring the testing mode of operation will be exactly the same as thesequence of sampled data words taken during the characterization mode ofoperation and which are stored in the data processor system. Todetermine if the UUT meets the standards of the known good unit, thesequence of currently sampled data words are sequentially compared, inthe compare function, with the sequence of stored sampled data words. Ifcoincidence exists between each successive pair of compared words, theunit is deemed to be good. However, if any pair of compared data wordsare not coincident, then the unit is deemed to be bad and, under controlof the master control logic, the test is terminated.

FEATURES OF INVENTION In accordance with a feature of the invention, thedata processor is employed at a relatively low data word rate, not onlyin the initialization mode of operation but also during thecharacterization mode when it is receiving samplings, and during thetesting mode when it is supplying said stored data words to the comparefunction means. On the other hand the circulation of data words aroundthe transfer loop, both during characterization and testing, occurs at avery high rate of speed substantially completely independent of thespeed capabilities of the data processor.

In accordance with another feature of the invention, the master controllogic is constructed to monitor the compare function means and tointerrupt the circulation of data around the transfer loop if the properstored data word from the data processor truth table has not beensupplied to the compare function at the time the corresponding sampledata word taken from the circulating data word is to be supplied to thecompare function. The foregoing is necessary since the input/outputdevice of the data processor is relatively slow compared to thecirculation rate of the data words around the transfer loop, and it ispossible that a sampled data word from the circulating data word couldbe supplied to the compare function before the data processor couldsupply the corresponding data word from its stored truth table.

FIGURES The above-mentioned and other objects and features of theinvention will be more fully understood from the following detaileddescription thereof when read in conjunction with the drawings in which:

FIG. 1 is a logic diagram of the basic concept of the invention;

FIG. 2 is a chart showing the basic steps involved in the processinvention;

FIG. 3 is another logic diagram showing the general organization of theoperating circuit and the master control logic which controls saidoperation;

FIGS. 4A, 4B, and 4C are a set of three figures showing the flow ofinformation in the system in each of the three basic modes of operation;e.g., initialization, characterization, and testing;

FIG. 5 is a more complex logic diagram of the invention adapted to testa UUT having a large number of input and output terminals and includingfor such purpose means for supplying a plurality of words to the UUT andmore specifically providing for separate circulating paths through orbetween the UUT and the transfer function;

FIG. 6 is a logic diagram of a logic circuit employed to effect theinitialization mode of operation which precedes both thecharacterization and the testing modes of operation;

FIG. 7 is a set of waveforms showing the operation of the inventionduring the initialization periods;

FIG. 8 is a logic diagram which shows a logic for generating the variousgating pulses required in the circulating loop during characterizationand initialization, with said logic providing for variable length gatingpulses in accordance with the particular test requirements of aparticular unit under test;

FIG. 9 shows a more detailed diagram of the compare function logic;

FIGS. 10 and 10A show a set of waveforms illustrating the operation ofthe circuit during characterization and testing modes;

FIG. 108 shows how FIGS. 10 and 10A fit together;

FIG. 11 is a logic diagram showing a pseudo-random generator utilized inthe transfer function of the invention;

FIG. 12 is a detailed logic diagram of a small portion of FIG. 10;

FIG. 13 shows a line design diagram of the transfer function includingthe pseudo-random generator of FIG. 10.

The specifications will be set forth in accordance with the followingorganization:

I. GENERAL DESCRIPTION A. IN ITIALIZATION MODE OF OPERATION (FIG. 1)

B. CHARACTERIZATION MODE OF OPERATION (FIG. 1)

C. TESTING MODE OF OPERATION (FIG. 1)

D. PROCESS (FIG. 2)

E. MASTER CONTROL LOGIC (FIG. 3)

F. MULTIPLE TRANSFER LOOP SYSTEM (FIG. 5)

l. Initialization Mode 2. Characterization Mode 3. Testing Mode II.DETAILED DESCRIPTION A. INITIALIZATION MODE OF OPERATION B.CHARACTERIZATION MODE OF OPERATION C. TESTING MODE OF OPERATION D.TRANSFER FUNCTION I. GENERAL DESCRIPTION Referring now to FIG. 1, thereis shown the logic diagram of the general organization of the invention.During a complete testing operation the logic of FIG. 1 actually formsthree different logic circuits; a first logic circuit effecting theinitialization mode, a second logic circuit for effecting thecharacterization mode of operation, and a third logic circuit forexecuting the testing mode of operation. Each of these logic circuitforms and the associated mode of operation will be consideredseparately.

IA. INITIALIZATION MODE OF OPERATION In the initialization mode, thelogic of FIG. 1 functions to place the electronic device being tested,designated by block 100, into a known state. As discussed briefly above,an initialization mode of operation occurs both before thecharacterization mode of operation and also before the testing mode ofoperation. In the initialization mode which occurs before thecharacterization mode, a unit of the type to be tested and known to be agood unit is positioned in the testing system as represented by block100. Such a unit, referred to herein generally as test unit, can beeither a known good unit, which is tested during the characterizationmode of operation to establish a reference set of data words, or it canbe a unit under test (UUT) which is tested during the testing mode ofoperation. Such a test unit can be any electronic device from a smalldigital component to a data processor system.

During the initialization period the data processor 101 functions tosupply a pre-programmed sequence of data words including instructionwords and initialization words to the system. More specifically theinitialization words are supplied to test unit through a circuitincluding serial-to-parallel converter 102, AND-gate 103, AND-gate 104,and input register 105. Such sequence of initialization words willperform the basic function of causing the test unit 100 (assumed at thispoint to be a known good unit) to assume a known condition from whichcharacterization will begin. It is to be noted that all subsequentlytested units of the same type as the known good unit will also beinitialized to the same known condition so that the testing thereof canbe compared with the characterization results of the known good unit.

The instruction data words, which actually precede the initializationdata words, function to set certain counters in the master control logicwhich function to control the test parameters during the initializationperiod and also during characterization and testing periods.

AND-gates 104 and 103, as well as AND-gates 106, 108, 110, and 112 arecaused to be opened or closed in accordance with a particular mode ofoperation of the circuit. In the initialization mode AND-gates 103 and104 are opened, i.e., conductive, and AND-gates 106, 108, 110, and 112are closed, i.e., nonconductive. The serial-to-parallel converter 102 isnot a necessary part of the invention and is employed only because thedata processor 101 is assumed to supply its output words in serial form,whereas the various modes of operation of testing one designed systememploy data words in parallel form. If a data processor capable ofsupplying and receiving words in parallel form were employed, then boththe serial-to-parallel converter 102 and the parallel-to-serialconverter 111 would be eliminated from the system and replaced withsimpler buffer storage devices.

The end of the initialization period is marked by some suitable meanssuch as, for example, an initialization counter (included in mastercontrol logic 115 but not specifically shown in FIG. I) initially set toindicate the number of words in the initialization mode, and decrementedby each supplied initialization data word. When such counter decrementsto zero the end of the initialization mode is thereby indicated and thecharacterization mode is initiated.

It should be noted that some suitable means, such as teletypewriter 119,is provided to enable an operator to communicate with the system throughthe data processor. The teletypewriter can be employed by the operator,for example, to

supply test parameters to the system, to initiate operation of thesystem, to receive information from the system indicating whether a testhas been successful or unsuccessful, and in general supply or receiveany information needed.

IB. CHARACTERIZATION MODE OF OPERATION In the characterization mode anew arrangement of the logic elements in FIG. 1 is made. Such newarrangement includes the test unit 100, AND-gate 106, output register107, AND-gate 108, transfer function 109, AND-gate 104 and inputregister 105 as well as gate 100 and converter 111. The output from dataprocessor 101 is cut off during the characterization mode by the closingof AND-gate 103.

The basic concept of the characterization mode is to circulate theinitially determined data word, left in the known good unit afterinitialization, through the transfer function 109 and then back throughthe known good unit, many times at a high rate of speed. The data wordis circulated in parallel form. AI- terations are made in said data wordeach time it passes through the known good unit, and each time it passesthrough the transfer function 109. The specific circuit path for thishigh-speed data word circulation can be traced from the known good unit100, through AND-gate 106, output register 107, AND-gate 108, transferfunction 109, AND-gate 104, input register 105 and back to known goodunit 100. The aforementioned circuit is identified herein both as aclosed loop circuit and also as the transfer loop.

The transfer function 109 functions to effect pseudo-random changes inthe data word each time said data word circulated therethrough. However,said pseudoqandom changes are the same for all good UUTs as they are fora known good unit thus providing a basis for comparing UUTs with theknown good unit during the testing mode of operation.

Sampling means contained in the master control logic 115 functions toperiodically sample the circulating data word by periodically openinggate 110 and supplying the circulating data word to serial-to-parallelconverter 11] and then to data processor 101, where sampled data wordsare stored, for later comparison with samplings of the circulating dataword through a UUT during the testing mode. Storage of such sampled datawords can be in the form of a truth table in main core in the processor,a magnetic tape, or other suitable bulk storage means under control ofthe processor.

The determination of which data words will be sampled and stored in saidtruth table is made by a cycle counter and a sample counter, notspecifically shown in FIG. 1 but included in the master control logicrepresented by block 115.

At this point it is appropriate to define a complete circulation of thedata word around the closed loop including the test unit 100 and thetransfer function 109. Such a cycle is defined as the propagation of adata word from output register 107, through AN D-gate 108, transferfunction 109, AND-gate 104, input register 105, test unit 100, and thenthrough AND-gate 106 back into the output storage register 107.

It should be noted that during a given cycle of the data word at leastthree clock pulses are required. The first clock pulse gates the datafrom the output register 107 through AND-gate 108 (assumed to be openduring the characterization mode), transfer function 109, AND-gate 104,which is gated open simultaneously with AND-gate 108, and into inputregister 105. A second clocking pulse, known as the UUT clock pulsesupplied from source 114 under control of master control logic 115 (notshown), is supplied internally to the test unit where it is utilized toopen certain predetermined gating cir cuits, shift certain shiftregisters, or to perform other desired functions. A third gating pulseknown as a strobe pulse is supplied to AND-gate 106 and functions tosupply the new data word appearing at the output of the test unit intooutput register 107. This strobe pulse completes a cycle of the dataword. During this cycle two changes have occurred in the data word, onechange occurring within transfer function 109 and the other changeoccurring within the test unit 100.

Returning again to the means for periodically sampling and storing thecirculating data word, there is provided a cycle counter (notspecifically shown in FIG. 1) which begins to count at the beginning ofcharacterization, and every Nth count thereof will function to openAND-gate 110, thereby supplying the data word occurring at that cycle todata processor 101 through parallel-to-serial converter 1 11.

Also provided in the master control logic 115, but not shownspecifically in FIG. 1, is a sample counter which counts the number oftimes that the cycle counter is to sample a data word and supply suchword through AND-gate and into data processor 101. Such sample counteris also'set at the beginning of initialization to the number of samplesdesired. Each time a data word is sampled and supplied to data processor101 the sample counter is decremented by one, until it eventuallyattains a count of zero, indicating the end of the characterization modeof operation. At this point in time there is stored in the dataprocessor a sequence of data words indicating the response of a knowngood unit and against which other units of the same type will becompared in order to determine if they are good or defective.

IC. TESTING MODE OF OPERATION Once characterization of the known goodunit has been completed, the testing of other units (UUTs) can begin.Such units are placed in the test position represented by block 100 andare first initialized in exactly the same manner as was the known goodunit.

At the end of the initialization the testing mode begins. The testingmode is quite similar to the characterization mode insofar as thecirculation of data from the UUT through transfer function 109 isconcerned. There is however a difference in the mannerin which thesampling of this data is effected and utilized.

More specifically, in the testing mode the circulating data word issampled at exactly the same corresponding times as was the circulatingdata word during characterization of the known good unit. However, inthe testing mode the sampled data words are not supplied to the dataprocessor 101 but rather are supplied to the compare function 113through AND-gate 112, which is periodically conductive during thetesting mode. The AND-gate l 10, conductive during sampling times incharacterization, is nonconductive during the testing mode.

The data words stored in the truth table are also supplied to comparefunction 113 from data processor 101 by means of converter 102 and gate103. It is to be noted specifically that the data words stored in thetruth table are supplied to compare function 113 one at a time and inthe same sequence as they were stored. Thus, the first data word sampledduring characterization will be compared with the first data wordsampled during testing, the second data word sampled duringcharacterization will be compared with the second word sampled duringtesting, and so on.

If the unit under test is a good unit, then each pair of words comparedshould coincide, indicating that the UUT is good. If, however, the UUTis defective, then the changes imposed upon the circulating word as itpasses through the UUT will be different than the changes imposedthereon when it passed through the known good unit duringcharacterization. All subsequent samples of the circulating data wordwill be different from corresponding data words in the truth table.Consequently the compare function 113 will show a non-coincidence,indicating a defective unit. Appropriate means are provided in themaster control logic 115 to terminate the test at this point. Such meansare not shown specifically in FIG. 1 but generally function to supply anerror-indicating signal to the parallel-to-serial converter 111, whichin turn will provide a signal to the data processor to terminate thetest. The test will also be terminated when the last sampling occurs andthe sample counter decrements to zero. Again the logic for suchtermination is not specifically shown in FIG. 1 but is effectedgenerally by signals supplied to the data processor 101 through theparallel-to-serial converter 111.

ID. PROCESS Referring now to FIG. 2, there is shown a flow chartillustrating the steps in the operation of the invention beginning withthe initialization and following with the characterization and/or thetesting sequence. Consider first the initialization mode which includessteps No. 1, No. 2, No. 3, No. 4, and No. 5. Step No. 1 functions to setthe initialization counter to the number of initialization words to besupplied by the data processor during the initialization sequence. Instep No. 2 a comparison portion of the cycle counter is set to apredetermined termination count which determines the number of cyclesbetween samples. In step No. 3 instruction words are supplied to set thesample counter in the master control logic, thereby determining thenumber of samples taken during the characterization or the testingmodes. More specifically the sample counter is set to some given number,for example 250, and decremented once each time the cycle counter cyclesthrough its maximum count. When the sample counter decrements to zerothe test is completed.

After the instruction words have been supplied to the system in stepsNo. 1, No. 2, and No. 3 of the initialization period, the initializingdata words are supplied to the test unit, as indicated in step No. 4.Decision logic, shown within block 129, is provided in the mastercontrol logic to check the initialization counter after eachinitialization word has been supplied to the system to determine if suchword is the last initializing word. If it is not the last initializingword, the master control logic functions through block 130 to cause thesystem to receive another initializing word.

The last initialization word is also used, as indicated by the doubledata flow arrow in FIG. 1, to initialize the transfer function 109.

When the last initializing word has been received, as indicated by theinitializing counter decrementing to zero, then step No. 6 commences, asdefined in block 131. If a known good unit is being tested thecharacterization cycle begins at this time. On the other hand, if a unitis being tested the testing cycle will commence. The cycle counterfunctions to count the number of cycles of the data word through thetransfer function. After N such cycles the sample counter is decrementedby one as indicated by step No. 7. As previously mentioned, duringinitialization a sample counter was set to a given value, as for example250, to determine the total number of samples to be taken duringcharacterization or testmg.

When the sample counter decrements to zero, the decision logic 133functions to effect step No. 8 to detect such condition and causes theend-of-test routine to occur, as indicated by block 134. However, untilthe sample counter decrements to zero the decision logic 133 willfunction to cause cycling to continue and the cycle counter to continueto count.

IE. MASTER CONTROL LOGIC Referring now to FIG. 3 there is shown anothergeneral block diagram of the invention, including a general logicdiagram of the master control logic. As indicated above, a plurality ofinput and output registers, as well as the single input and outputregisters, can be employed in those cases where the number of inputterminals and output terminals of the UUT are large. Thus in FIG. 3 theinput register means 150 and the output register means 152 are showngenerally and can each represent either one register or a plurality ofregisters, such as is shown in FIGS. and 6, for example. The blocks 150and 152 also represent the input, output, and strobe gates connectedthereto and represented generally in FIG. 1 by reference characters 104,106, and 108.

As can be seen from FIG. 3, the same logic blocks are shown therein asare shown in FIG. 1. More specifically, FIG. 3 shows a transfer functionof 109', a compare function 113', a data processor 101', aserial-to-parallel converter 102', a parallel-to-serial converter 111'and a UUT 101). Also shown in FIG. 3 are several of the gates shown inFIG. 1, such as AND-gates 112', 110', and 103'.

In addition there is shown in FIG. 3 a general block diagram of themaster control logic which includes initialization counter andassociated logic 154, the cycle counter 156, and sample pulse counter157.

Also shown in FIG. 3 are means to end the test including an AND-gate 159which responds to an end-of-test signal from processor 101, and aswitching means such as flip-flop 160 which responds to the output ofthe AND-gate 159 to disable AND-gate 161 and thereby terminate thecirculation of the data through transfer function 109 and UUT Suchend-of-test signal can come about in one of two ways. Firstly, it canoccur as a result of a normal test completion where the UUT has provento be good and the sample counter has decremented to zero. In this casea signal is supplied from sample pulse counter 157 at the count of zero,through lead 171 to the parallel-to-serial converter 111, which isconstructed to respond to such a signal to generate and supply a dataword to the data processor 101' indicating the end of test. The dataprocessor in turn responds to such word to generate an end-of-testsignal which is supplied via the serial-to-parallel converter 102', andAND-gate 159 to set flip-flop 160, thereby disabling AND-gate 161 andinterrupting the circulation of data through the transfer function 109'.

The second means by which the test can be terminated is bynon-coincidence of a data test word and the corresponding word from thetruth table in processor 101'. Under such conditions the compare circuit113' will supply a signal via lead 172 through the parallel-to-serialconverter 1 11' to processor 101' indicating that the unit is defectiveand that the test should be aborted. The processor 101' will thengenerate an end-of-test signal which will be supplied through AND-gate159 to set flip-flop and disable AND-gate 161.

Consider now the relation between the initialization counter, the cyclecounter and the sample pulse counter. At the beginning of theinitialization mode, an instruction word is supplied from the processor101' to the initialization counter in logic block 154 through AND-gate103, which is enabled during initialization. The initialization logicresponds to the instruction word to enable setting of the initializationcounter, the cycle counter 156 and the sample pulse counter 157 with thenext several instruction words, as indicated generally in the logic flowdiagram of FIG. 2. More specifically the first instruction word afterthe initialization mode address of word can function to set theinitialization counter to the number of initialization words to beemployed. The following two instruction words can be then employed toset the cycle counter to zero and also to set the maximum count of thecycle counter. The next instruction word can be employed to set thesample pulse counter to the number of samples to be taken during thecharacterization and the test modes. Logic means, not shown specificallyin FIG. 3, are employed to sequentially route successive instructionwords from the initialization counter to the cycle counter and then tothe sample pulse counter.

It is to be understood that the setting of the initialization counter,the cycle counter and the sample pulse counter all occur during thefirst part of the initialization mode. During this part of the operationthe AND-gate 103 is conductive and AND-gates 112 and 110 arenonconductive. Also, as will be shown later, the AND gates associatedwith the input and output terminals of the output registers 152 are bothnonconductive since no circulation of data words through the transferfunction 109' occurs during the initialization period. The onlytransmission of data words is from processor 101' into the mastercontrol logic including the initialization counter in logic 154, thecycle counter 156 via input and the sample counter 157 via input 176.Data words are subsequently supplied into UUT 100' through inputregister means 150.

Some means are required to indicate the completion of a cycle of datacirculation during the characterization and testing modes in order forthe cycle counter 156 to count. Such means is provided via lead 178 toAND-gate 155. While the precise derivation of the cycle completionpulses appearing on input 178 will be explained later herein, it willsuffice for the present to state that a pulse will be supplied to inputlead 178 at the completion of a cycle, as defined hereinbefore, and suchcycle completion pulse will pass through AND-gate 155, during thecharacterization and testing modes, into cycle counter 156 where thecycles are counted. It is to be understood that the other input lead 179to AND-gate 155 will have a signal thereon during the characterizationand testing modes, thereby enabling AND-gate 155 during these two modesof operation. A specific logic by which the foregoing can beaccomplished is as follows. The initialization counter 154 is originallyset to some number which is equal to the number of initialization words.When the initialization counter decrements to zero the. initializationis complete, and a signal appears on lead 179 to enable AND-gate 155.

As discussed briefly above there are differences between thecharacterization and testing modes of operation of the system. Duringthe characterization mode AND-gate 110' must be open at specific timesso that the sampled data words are supplied to processor 101' throughparalleI-to-serial converter 111'. During this characterization modeAND-gate 112' must be disabled since no comparison is to occur. On theother hand during the testing mode comparison does occur but no datawords are to be supplied to processor 101. Consequently, during thetesting mode AND-gate 110' is disabled and AND-gate 112' is enabled.Such switching of AND-gates 110' and 112 is accomplished by means ofswitch 165, which can be a manual switch preset by the operator prior toinitialization. If characterization is to follow initialization, themovable arm of switch 165 is made with contact C. If testing is tofollow initialization, the armature is made with contact T.

While the switch 165 can be manually set by an operator since there isordinarily an interval of time between characterization and the testingof UUT, it is apparent switch 165 could also be an electronic switchautomatically set from the C-contact to the T-contact upon completion ofthe characterization mode, and remain in the test mode with contact Tthereafter. Such an electronic switch could be in the form of a simpleflip-flop circuit originally set by the operator in a first position tocause characterization to occur, and then, upon completion ofcharacterization, as indicated by the first decrementation of the samplecounter to zero, for example, to be reset and remain reset thereafterthrough multiple testing operations, until again manually set by theoperator for a new characterization.

Referring now to FIGS. 4A through 4C there are shown the data paths forthe three basic modes of operation. More specifically, in FIG. 4A thereis shown the data flow path during the initialization mode, in FIG. 4B,the data flow path during characterization, and in FIG. 4C, the dataflow path during the testing mode. It is to be noted that in each of thethree FIGS. 4A, 4B, and 4C the flow of data at the relatively low rateof the data processor is shown in heavy dotted lines and the flow ofdata at the high-speed rate through the transfer loop is shown in lightdotted lines.

In FIG. 4A the initialization instruction data words are supplied at alow rate of speed from suitable bulk storage means, such as a magnetictape unit 206 under control of data processor 205 having a main corememory 210. The data is then supplied through a portion of the feedbacksequence control circuit 210 (which includes the master control logic204, the transfer function 203 and the compare function 202), to thedevice being tested 200, which can be either a known good unit or a UUT.

In FIG. 48 there is shown the data flow for the characterization mode ofoperation. It can be seen that in FIG. 48 there are both low speed andhigh-speed rates of data transmission. The high-speed data rate pathextends around the transfer loop 211 which includes the UUT 200, or incase of characterization the known good unit, and the transfer loop203', as well as input and output registers and AND gates associatedtherewith but not shown in FIGS. 4A, 4B, and 4C.

The low speed data transmission path extends from transfer function 203,to tape unit 206' through data processor 205.

This low speed data comprises the data word sampled periodically fromthe data word circulating around the transfer loop and supplies saidsampled data words to tape unit 206' to form the truth table which lateris used for comparison with similar sampled data words during testing ofa UUT.

In FIG; 4C, which shows the data paths for the testing mode, ahigh-speed data path exists around the closed loop circuit including theUUT 200" and the transfer function 203". There is also a slow-rate datapath from the transfer loop 211 to compare circuit 204" and designatedby reference character 207. A second slow-rate data path 208 exists fromtape unit 206", under control of data processor 205", to compare circuit204". As discussed above the compare circuit functions to compare thesetwo data signals for coincidence.

A third slow-rate data path 209 exists between compare circuit 204" anddata processor 205", and specifically is the path for the signalterminating a test, either because of noncoincidence in the comparisonfunction 204 or because the test has been successfully completed.

IE. A MULTIPLE TRANSFER LOOP SYSTEM (FIG. 5)

Referring now to FIG. 5, there is shown a form of the invention capableof testing units which have large numbers of input and output terminals.With such units the number of input and output terminals frequentlyexceed the number of bits in the data processor output words. Forexample, in the structure of FIG. 1, it is assumed that the dataprocessor outputs in serial manner 12-bit words, and that two of thesewords are assembled in the serial-to-parallel converter 102 and thensupplied to the UUT in parallel form as a single 24-bit word. In thecase of UUTs having more than 24 input terminals or 24 output terminals,it is necessary to employ additional logic to supply test data words tothe UUT. Such additional logic is shown in FIG. 5 and essentiallyfunctions to perform a type of multiplexing.

More specifically in FIG. 5 there are shown four input registers 240,241, 242, and 243 and four output registers 244, 245, 246, and 247associated respectively with the input terminals and the outputterminals of the UUT A group of AND-gates 258, 259, 260, and 261 connectthe output ofdata processor 101" to the four registers 240 through 243,respectively.

. Each of the four output registers 244 through 247 has an AND gate atits input and an AND gate as its output terminal. The AND gates at theinputs of output registers 244-247 are designated by referencecharacters 248 through 251 and the AND gates at the output terminalsthereof are designated by reference characters 252 through 255. Theoutputs of the four output AND-gates 252-255 are supplied to a commonOR- gate 256 whose output is in turn supplied to transfer function 109",the compare circuit 113" and to the parallel-to-serial converter 111",all through appropriate gating networks.

It is to be noted that each of the double-lined leads, such as lead 215,represents 24 individual conductors. The only exceptions in FIG. 5 arethe-double-lined leads 216, 296, and 193, each of which represents fourindividual conductors running from register 217, lead 334 and selectormeans 270 respectively, each of which will be discussed in detail laterherein.

Also shown in FIG. 5 are two interface adapters 194 and 195 whichinterface the input and the output of the UUT 100" with the testapparatus. The said interface adapters 194 and 195 function toaccommodate the various impedance, voltage, and current requirements ofdifferent UUTs to the voltage and impedance characteristics of thetesting apparatus. For example, MOS circuits require quite differentvoltage and impedance levels than do 'III. type circuits or othersemi-conductive type circuits. It is apparent that different interfaceadapters are required for almost every different type electronic device,since voltage and impedance levels, as well as the number of input andoutput terminals, are different for different electronic devices.

Furthermore, even with a given type UUT it is sometimes desirable, fortest purposes, to be able to vary voltage levels to

1. A method of testing electronic devices comprising the steps of:initializing a known good electronic device of the type to be tested bysupplying a first predetermined sequence of data words to said knowngood electronic device to place said known good device in apredetermined condition; circulating a second sequence of data words,starting with a given data word, around a loop comprising said knowngood unit and a transfer function; altering said circulating data wordsby said transfer function to provide a sequence of repeatablealterations on said circulating data word for all electronic deviceswhich respond in the same manner to data words circulating therethrough;sampling said data word every Nth circulation thereof; storing saidsampled data words; initializing an electronic device to be tested tohave the same predetermined condition as said known good device afterinitialization; circulating a third sequence of data words, startingwith said given data word, around said loop comprising said electronicdevice being tested and said transfer function; sampling said thirdsequence of circulating data every Mth circulation thereof; andcomparing said Mth sampled circulating data word of said third sequenceof circulating data words with the Nth sampled stored data of saidsecond sequence of circulating data words to determine coincidence ornon-coincidence of said data words being compared, where M representstime-corresponding successive samplings.
 2. The method of testingelectronic devices with testing equipment comprising the steps of:initializing a known good unit to a predetermined condition;characterizing said known good unit; initializing a unit under test tosaid predetermined condition; testing said unit under test; saidinitializing steps each comprising the steps of; supplying apredetermined sequence of instruction words to the testing equipment toprepare said testing equipment for characterization or testing; andsupplying a predetermined sequence of data words to the unit under testto place said unit under test in said predetermined condition; saidcharacterizing step and said testing step each comprising the steps of;circulating a predetermined data word around a loop comprising the unitunder test and a transfer function; and altering the data words as theypass through said transfer function in a repeatable manner in responseto any given sequence of data words supplied thereto; and comparing atleast one of the resulting data words in said characterizing step withthe corresponding data words in the testing step.
 3. A method of testingelectronic devices comprising the steps of: initializing a known goodelectronic device of the type to be tested to place said known gooddevice in a predetermined condition; circulating a first sequence ofdata words, starting with a given data word from the output means of theknown good electronic device, through a data word transfer functionhaving a given initial condition, and back to the input means of theknown good electronic device; mutually altering the circulating dataword and the transfer function by each other each circulation of thedata word through the transfer function to produce at the output of saidtransfer function a sequence of repeatable data words for all electronicdevices which respond in the same manner to data words circulatingtherethrough; sampling said first sequence of circulating data words inpredetermined counts of circulations thereof; storing said sampled datawords; initializing an electronic device to be tested to have the samepredetermined condition as said known good device after initialization;circulating a second sequence of data words, starting with said givendata word, from the output means of said electronic device being tested,through said transfer function having said initial given condition, andback to the input means of said electronic device being tested; samplingsaid second sequence of circulating data words for the samepredetermined counts of circulation thereof as for the first sequence ofsampling; and comparing said sampled data words of said second sequenceof circulating data words with the corresponding sampled stored datawords of said first sequence of circulations of data words to determinecoincidence or non-coincidence of said data words being compared.
 4. Amethod of testing electronic devices comprising the steps of;initializing a known good electronic device of the type to be tested toplace said known good device in a predetermined condition; circulating afirst sequence of data words, starting with a given data word, around aloop comprising said known good unit and a transfer function; mutuallyaltering the circulating data word and the transfer function by eachother each circulation of the data word through the transfer function toproduce at the output of said transfer function a sequence of data wordswhich is repeatable for all electronic devices which respond in the samemanner to data words circulating therethrough; sampling every Nthcirculation of said circulating data word; storing said sampled datawords; initializing an electronic device to be tested to have the samepredetermined condition as said known good device after initialization;circulating a second sequence of data words, starting with said givendata word, around said loop comprising said electronic device beingtested and said transfer function; sampling said second sequence ofcirculating data every Mth circulation thereof; and comparing said Mthsampled data word of said second sequence of circulating data words withthe Nth sampled stored data word of said first sequence of circulatingdata words to determine coincideNce or non-coincidence of said datawords being compared.
 5. A method of testing electronic devicescomprising the steps of: initializing a known good electronic device ofthe type to be tested by supplying a first predetermined sequence ofdata words to said known good electronic device to place said known gooddevice in a predetermined condition; circulating a second sequence ofdata words, starting with a given data word, around a loop starting fromthe output of the known good unit and ending at the input thereof;sampling said data word in a predetermined sequence of circulations ofthe data words; storing the sampled data words; initializing anelectronic device to be tested to have the same predetermined conditionas said known good device after initialization; circulating a thirdsequence of data words, starting with said given data word, around saidloop comprising said electronic device being tested; sampling said thirdsequence of circulating data words in the same predetermined sequence ofcirculations as the known good unit was sampled; and comparing thecorresponding sampled circulating data words of the third sequence ofcirculating data words with the sampled stored data of said secondsequence of said circulated data words to determine the identity of saiddata words being compared.
 6. A method for testing electronic devicescomprising the steps of: initializing a known good electronic device ofthe type to be tested to a predetermined condition; characterizing saidknown good unit to produce a sequence of data words of which every Nthdata word is stored; initializing an electronic device to be tested toproduce said predetermined condition; testing said electronic device toproduce a second sequence of data words; comparing for coincidence eachsuccessive Nth data word of said second sequence of data words with eachsuccessive data word of said stored Nth data words.
 7. A method fortesting electronic devices comprising the steps of: initializing a knowngood electronic device of the type to be tested to a known,predetermined condition; circulating for P circulations an initiallydetermined data word through said known good electronic device andthrough a transfer function which, when in any given condition, willalways alter any given data word in the same way; sampling saidcirculating data word every Nth circulation thereof; storing saidsampled data words; initializing an electronic device to be tested tosaid known, predetermined condition; circulating for P circulations saidinitially determined data word through said electronic device beingtested and through said transfer function; sampling said circulatingdata word circulating through said electronic device being tested everyNth circulation thereof; comparing for coincidence each successivesampled data word with the corresponding successive stored sampled dataword.
 8. A testing system for digitally testing electronic deviceshaving an initialization mode of operation, a characterization mode ofoperation, and a testing mode of operation, and comprising; first meansfor supplying a sequence of initializing instruction data words, and asequence of initializing data words, and for receiving, storing, andsupplying a sequence of sampled data words; test station means forelectrically connecting one of said electronic devices into said testingsystem; transfer function means; compare function means; master controllogic means, responsive to said initialization instruction data words,for supplying said initialization data words to said electronic devicefor initializing said electronic device to a given condition and foridentifying the end of the initialization mode of operation; said mastercontrol logic means further constructed to respond to the end of saidinitialization mode of operation to form a closed loop circuitcOmprising said electronic device and said transfer function means, tocause an initially determined data word to circulate in said closed loopcircuit, and to sample said circulating data word every Nth circulationthereof; said master control logic further comprising switching meanshaving first and second states and constructed, when in a first state,to supply said sampled data words to said first means to be storedtherein, and when in a second state to supply said sampled data words tosaid compare function means; said first means further constructed torespond to the second state of said switching means of said mastercontrol logic to supply sequentially, and in the same order in whichthey were stored, the data words stored therein to said compare functionmeans, with each Nth stored sampled data word being present in saidcompare function means during a time interval coincident with thepresence in said compare function means of the Nth sampled data word ofthe circulating data word, where M represents any giventime-corresponding sampling; said compare function means constructed tocompare the stored sampled data words and the sampled circulating datawords supplied thereto for coincidence therebetween.
 9. A testing systemin accordance with claim 8 comprising in addition; first storage meansconnected, during the initialization mode of operation, between theoutput of said data processor means and said electronic device; andgating means responsive to the supplying of data words from said dataprocessor means to become conductive to pass said data words into saidfirst storage means; and means for clocking said data words stored fromsaid first storage means into said electronic device.
 10. A testingsystem in accordance with claim 8 comprising; first storage meansconnected, during said characterization mode of operation and duringsaid testing mode of operation, between the output of said transferfunction means and the input of said electronic device; second storagemeans connected, during said characterization mode of operation andduring said testing mode of operation, between the output of saidelectronic device and the input of said transfer function means; saidmaster control logic means comprising timing means; gating meansresponsive to said timing means for progressively circulating a dataword around the said closed loop circuit which comprises said secondstorage means, said transfer function means, said first storage means,and said electronic device.
 11. A testing system in accordance withclaim 8 in which; said master control logic means and said first meansare each constructed to respond to a comparison in said compare functionmeans, of a sampled data word from said circulating sequence of datawords and a stored sampled data word from said data processor beforesupplying another sampled data word to said compare function means. 12.The apparatus of claim 8 wherein the transfer function means includesmeans for randomizing the data word as it passes therethrough.
 13. Atesting system in accordance with claim 8 in which said master controllogic means further comprises; first storage means responsive to saidinstruction data words to store the number of initialization data wordsto be supplied from said data processor means during said initializationmode of operation and to decrement said stored number by a predeterminednumber each time an initialization data word is supplied from said dataprocessor means; counter means responsive to said instruction data wordsto become conditioned to count the number of data word circulationsaround said closed loop circuit between samplings and to indicate whensuch samplings are to be made; and second storage means responsive tosaid instruction data words to store the number of samplings to be madeduring each of the characterization mode of operation and the testingmode of operation, and to decrement said Stored number each sampling ofthe data word during the characterization or testing modes of operation.14. A testing system in accordance with claim 13 comprising in addition;third storage means connected, during said characterization mode ofoperation and during said testing mode of operation, between the outputof said transfer function means and the input of said electronic device;fourth storage means connected, during said characterization mode ofoperation and during said testing mode of operation, between the outputof said electronic device and the input of said transfer function means;said master control logic means comprising timing means gating meansresponsive to said timing means for progressively circulating a dataword around the said closed loop circuit which comprises said fourthstorage means, said transfer function means, said third storage means,and said electronic device.
 15. A testing system in accordance withclaim 14 in which; said third storage means comprises a plurality offifth storage means, with each of said fifth storage means connectedbetween the output of said transfer function and a different group ofinput terminals of said electronic device; said fourth storage meanscomprises a plurality of sixth storage means with each of said sixthstorage means being connected between a different group of outputterminals of said electronic device and the input of said transferfunction means; said gating means comprises a plurality of gating meansconstructed to form a plurality of closed loop circuits with each closedloop circuit comprising said transfer function means, said electronicdevice and one each of said fifth and sixth plurality of storage means;and in which said master control logic means comprises selecting meansfor successively selecting each of said closed loop circuits forcirculating the data completely around each selected closed loop circuitbefore selecting and circulating the data around the next selectedclosed loop circuit.
 16. A testing system in accordance with claim 15comprising, in addition; timing means constructed for circulating saiddata word around said closed loop circuit at selectable rates of speed.17. A testing system in accordance with claim 14 in which; said thirdstorage means comprises a plurality of fifth storage means, with each ofsaid fifth storage means connected between the output of said transferfunction and a different group of input terminals of said electronicdevice; said fourth storage means comprises a plurality of sixth storagemeans with each of said sixth storage means being connected between adifferent group of output terminals of said electronic device and theinput of said transfer function means; said gating means comprises aplurality of gating means constructed to form a plurality of closed loopcircuits with each closed loop circuit comprising said transfer functionmeans, said electronic device and one each of said fifth and sixthplurality of storage means; and in which said master control logic meanscomprises selecting means for successively selecting each of said closedloop circuits and for circulating the data completely around eachselected closed loop circuit before selecting and circulating the dataaround the next selected closed loop circuit.
 18. A testing system inaccordance with claim 13 comprising, in addition; timing meansconstructed for circulating said data words around said closed loopcircuit at selectable rates of speed.
 19. A testing system for digitallytesting electronic devices having initialization, characterization, andtesting modes of operation and comprising; data means for supplying afirst sequence of instruction words to condition said testing system fora given initialization mode of operation and a given characterization ortesting mode of operation and for supplying data words to initialize oneof said electronic devices to a known condition; transfer functionmeans; control means for circulating an initially determined data wordaround a closed loop circuit comprising said transfer function means andsaid electronic device; means for sampling said circulating data wordevery Nth circulation thereof around said closed loop circuit; comparefunction means; means for selectively supplying said sampled data wordsto one of said compare function means and said data processor means;said data processor means constructed to store said received sampleddata words; means for consecutively supplying said stored sampled datawords to said compare function means in the same order in which theywere received and stored and at times coincident with the supplying ofcorresponding currently sampled circulating data words to said comparefunction means; said compare function means constructed to compare thestored sampled data words and the sampled circulating data wordssupplied thereto for coincidence; means responsive to non-coincidencebetween a stored data word and a currently sampled circulating data wordin said compare function means to supply an error signal to said dataprocessor means.
 20. A testing system in accordance with claim 19 inwhich; said control means and said data means are each constructed torespond to a comparison, in said compare function means, of a sampleddata word from said circulating sequence of data words and a storedsampled data word, before supplying another sampled data word to saidcompare function means.
 21. The apparatus of claim 19 wherein thetransfer function means includes means for randomizing the data word asit passes therethrough.
 22. A testing system in accordance with claim 19comprising: first storage means connected, during the initializationmode of operation, between the output of said data means and saidelectronic device; and gating means responsive to the supplying of datawords from said data means to become conductive to pass said data wordsinto said first storage means; and means for clocking said data wordsstored from said first storage means into said electronic device.
 23. Atesting system in accordance with claim 19 comprising; first storagemeans responsive to said instruction words to store a first given numberof initialization data words to be supplied from said data means duringsaid initialization mode of operation and to terminate the supplying ofinitialization data words when the given number of initialization datawords have been supplied from said data means; counter means responsiveto said instruction words to become conditioned to count the number ofdata word circulations around said closed loop circuit between samplingsand to indicate when such samplings are to be made; and second storagemeans responsive to said instruction data words to store a second givennumber of samplings to be made during each of the characterization modeof operation and the testing mode of operation, and to terminate thepresent characterization or testing mode of operation when said secondgiven number of samplings has occurred.
 24. A testing system inaccordance with claim 23 comprising; third storage means connected,during said characterization mode of operation and during said testingmode of operation, between the output of said transfer function meansand the input of said electronic device; fourth storage means connected,during said characterization mode of operation and during said testingmode of operation, between the output of said electronic device and theinput of said transfer function means; timing means; gating meansresponsive to said timing means for progressively circulating a dataword around the said closed loop circuit which comprises said fourthstorage means, said transfer function means, said third storage means,and said electronic device.
 25. A testing system in accordance withclaim 24 in which; said third storage meAns comprises a plurality offifth storage means, with each of said fifth storage means connectedbetween the output of said transfer function means and a different groupof input terminals of said electronic device; said fourth storage meanscomprises a plurality of sixth storage means with each of said sixthstorage means being connected between a different group of outputterminals of said electronic device and the input of said transferfunction means; said gating means comprises a plurality of gatesconstructed to respond to said timing means to form a plurality ofclosed loop circuits, with each closed loop circuit comprising saidtransfer function means, said electronic device and one each of saidfifth and sixth plurality of storage means; and comprising selectingmeans for successively selecting each of said closed loop circuits andfor circulating the data completely around each selected closed loopcircuit before selecting and circulating the data around the nextselected closed loop circuit.
 26. A testing system in accordance withclaim 19 comprising; first storage means connected, during saidcharacterization mode of operation and during said testing mode ofoperation, between the output of said transfer function means and theinput of said electronic device; second storage means connected, duringsaid characterization mode of operation and during said testing mode ofoperation, between the output of said electronic device and the input ofsaid transfer function means; timing means; gating means responsive tosaid timing means for progressively circulating a data word around thesaid closed loop circuit which comprises said second storage means, saidtransfer function means, said first storage means, and said electronicdevice.
 27. A testing system in accordance with claim 26 in which; saidtiming means is constructed to circulate said data word around saidclosed loop circuit at selectable rates of speed.
 28. A testing systemin accordance with claim 26 in which; said first storage means comprisesa plurality of third storage means, with each of said third storagemeans connected between the output of said transfer function and adifferent group of input terminals of said electronic device; saidsecond storage means comprises a plurality of fourth storage means witheach of said fourth storage means being connected between a differentgroup of output terminals of said electronic device and the input ofsaid transfer function means; said gating means comprises a plurality ofgates constructed to respond to said timing means to form a plurality ofclosed loop circuits, with each closed loop circuit comprising saidtransfer function means, said electronic device and one each of saidthird and fourth plurality of storage means; and comprising selectingmeans for successively selecting each of said closed loop circuits andfor circulating the data completely around each selected closed loopcircuit before selecting and circulating the data around the nextselected closed loop circuit.
 29. A testing system in accordance withclaim 28 in which; said timing means is constructed to circulate saiddata word around said closed loop circuit at selectable rates of speed.30. Apparatus for digitally testing electronic units comprising, incombination: unit input and unit output means for connection to a unitto be tested; first means for supplying initializing data words;switching means connected to said unit input means, said unit outputmeans and said first means for first supplying said initializing datawords to a unit to be tested via said unit input means and forsubsequently circulating data words from said unit output means to saidunit input means; second means for sampling said circulating data wordsat predetermined intervals; storage means, connected to said secondmeans, for storing the sampled data words obtained from testing areference known good unit; comparison means, connected to said storagemeans, and said second means, for comparing the stored sample data wordsfrom the reference known good unit with time corresponding sample datawords from the unit being tested; and apparatus output means forproviding an indication of the comparison.
 31. Apparatus for testingelectronic devices comprising in combination: first means for supplyinga given sequence of initializing instruction data words and a sequenceof initializing data words, and for receiving, storing, and supplying asequence of sampled data words; second means for comparing two inputs;third means connected to said first means for initially causing saidfirst means to supply said sequence of initializing instruction datawords to a unit to be tested and then causing said first means tocirculate the resulting data words in a closed loop circuit, said thirdmeans sampling the circulating data word at predetermined circulationintervals thereof, said third means being further connected to saidsecond means for supplying sampled data words thereto indicative ofsignals obtained from a known good unit and supplying the sampled datawords from the unit under test to said second means in the same order asoriginally obtained for comparison within said second means; and outputmeans for providing an indication of the comparison function.